1. Field of the Invention
The present invention relates to an integrated circuit package and a manufacturing method thereof and particularly to a fan-out structure of a wafer level package and a method of manufacturing the same.
2. Description of the Related Art
According to a recent trend of improving to achieve light-weight and compact parts, a wafer level package (WLP) technology is being introduced as a way of achieving this in the package assembly field. Being different from the conventional process in that every single chip separated from a wafer is packaged on one-by-one basis, the wafer level packaging makes it possible to finish the assembly process on the wafer without separating the chip. Briefly, there are four steps in this technology which are: circuit designing, wafer treating, assembling, and inspecting for the completion of the semiconductor manufacturing process. Among these steps, the assembling, which includes wire bonding and packaging, is performed by dicing the chip from the processed wafer; attaching the respective chip to a small substrate; bonding wire; and packaging the chip with plastic material. However, in the wafer level packaging, the packaging process is simply performed by initially applying photo-sensitive insulating materials to each of chips on the wafer instead of the conventional plastic material for packaging. Thereafter, the packaging process is finished by bonding the wire and applying the insulating material.
With the application of the above packaging technology, the semiconductor assembly process including the steps such as the wire bonding and the plastic material packaging may be eliminated. Furthermore, a significant reduction of cost can be attained because the plastic material, a circuit board and the bonding wire and etc. are not necessary. Particularly, the size of the package can be reduced by 20% in comparison to a conventional chip scale package (CSP) which has been employed in miniaturization efforts of the semiconductor. This is because it is possible to manufacture the package at the same size as the chip. Additionally, the existing wafer assembling facility and process can be employed in the manufacturing facility and process of the wafer level package.
On the other hand, as a part of multi-function and small-sized package technology in the next generation, attention has been recently paid to the development of a printed circuit board with a built-in IC (electronic device). In addition to the advantages such as the multi-function and small-sized package, the printed circuit board with the built-in IC provides more functions. It is not only because the wiring distance can be minimized in a high frequency above 100 MHz, but because there is a solution for improving the reliability problem which are associated with the connection of the parts using bonding wire or solder ball, which is adopted in a flexible circuit board or a ball grid array.
FIG. 1 is a cross-sectional view of an integrated circuit package according to a conventional technology.
FIG. 1 is a wafer level package using multi-layered PCB. As shown, an IC chip 10, which includes on its upper face a plurality of input/output pads 11 for electrical connection, is disposed within a cavity in an insulating layer 20 corresponding to a core insulating layer of the multi-layered PCB. The multi-layered PCB includes a plurality of the insulating layers 20 to 28 and a plurality of conductive patterns, which are stacked in alternate and repetitive manner. A via-hole is formed through the insulating layers 20 to 28. The electrical connection is made through the via-hole. In FIG. 1, the plurality of the input/output pads 11 is connected to outer terminals through solder-ball lands 31a, 31b, 32a, 32b, 33a, and 33b, the via-hole, and connection leads 31, 32, and 33. For the sake of convenience in illustration, the via-holes formed in each of the insulating layers 22 and 23 are omitted in the drawings.
FIG. 2 is a perspective top view illustrating the fan-out structure of the wafer level package shown in FIG. 1. FIGS. 3A, 3B and 3C are top views illustrating the fan-out structure in each of layers shown in FIG. 1.
Referring to FIGS. 2, 3A, 3B and 3C, the fanned-out type solder-ball lands 31a and 31b, 32a and 32b, and 33a and 33b are arranged in double rows on each of the insulating layers, thus three insulating layers are needed for the fan-out structure.
The sizes of the solder-hall and the bump are limited by the size of the via-hole formed in the PCB because the conventional wafer level package is electrically connected to the PCB through the via-hole. In other words, as the sizes of the solder ball and the bump are enlarged, they impose the restriction on increasing the amount of the input/output pads. Further, as a larger number of layers is needed when mounting on the embedded-type PCB, the total thickness of the PCB is unfavorably increased.